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1 / 27 semiconductor m l670100 oki ? s high-performance cmos 32-bit single chip microcontroller general description the ML670100 is a high-performance 32-bit microcontroller combining a risc based, 32-bit cpu core - the arm7tdmi tm - with memory and such peripheral circuits as timers, serial ports, and analog-to- digital converter. this combination of 32-bit data processing, built-in memory, and on-chip peripherals make it ideal for controlling equipment requiring both high speed and high functionality. an external memory controller supports direct connection to memory and peripheral devices for adding even more functionality. features operating voltage 2.7 to 3.6v operating frequency 25mhz maximum(3.0 to 3.6v) on-chip memory -rom: 128 kilobytes -ram: 4 kilobytes i/o function i/o ports: 8 bits x 9, i/o directions are specified at the bit level timer -flexible timer (16-bit multi-function timer with six channels) choice of operating modes: auto-reload timer, compare output, pwm and capture -time base counter with wdt function serial port -one asynchronous serial port (uart) with baud rate generator -two clock synchronous serial port a-to-d converter -8-bit resolution a-to-d converter with eight analog input ports interrupt controller -support for 28 interrupt sources: 9 external and 19 internal -choice of eight priority levels for each source external memory controller -direct connection to rom, sram, dram and peripheral devices -support for four banks: two for rom, sram and i/o devices plus two for dram -user-configurable bus width (8/16 bits) and wait control and other parameters for accessing memory and external devices clock generator -built-in crystal oscillation circuit and pll -choice of divider ratio (1/1, 1/2, 1/4) for adjusting operating clock frequency to match the load of processing package 144-pin lqfp ( lqfp144-p-2020-0.50-k) arm powered logo is the registered trademark of arm limited. arm7tdmi is the trademark of arm limited. the information contained herein can change without notice owing to product and/or technical i mprovement. the signal name of negative logic is being changed to nxxx from xxx in this data sheet. version 2 aug., 1999
semiconductor m l670100 / 27 2 block diagram aste risks indicate signals that are se condary functions of i/o ports. brackets indicate bit ranges. arm7tdmi 4 kilobytes of ram 128 kilobytes of rom time base generator (tbg) flexible timer asynchronous serial interface (asi) clock synchronous interface (csi0 and csi1) interrupt controller (int) analog-to-digital converter (adc) internal bus controller external memory controller (xmc) i/o ports tdi* tdo* n trst* tms* tck* dbgen* dbgrq* dbgack* xa23-16* xa15-1 n lb/xa0 xd15-8* xd7-0 n cs0 n rd n wre/ n wrl n xwait* n cs1* n hb/ n wrh* n ras1* n wh/ n cash* n ras0* n cas/ n casl* n wl/ n we* n breq* n back* n rst n ea dbsel test vdd gnd avdd agnd tmin/tmout[5:0]* tmclk[1:0]* asi_txd* asi_rxd* csi1_txd* csi1_rxd* csi1_sclk* csi0_txd* csi0_rxd* csi0_sclk* n efiq n eir[7:0]* vref ai[7:0] clock control osc0 osc1 clkout fsel pllen vcom pio8[7:0] pio7[7:0] pio6[7:0] pio5[7:0] pio4[7:0] pio3[7:0] pio2[7:0] pio1[7:0] pio0[7:0] core data bus (32b) peripheral data bus 16b) core address bus peripheral address bus
semiconductor m l670100 / 27 3 pin configuration (top view) top view index mark 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 ai[4] ai[3] ai[2] ai[1] ai[0] vref avdd vdd test dbsel pio6[0] pio6[1] pio6[2] pio6[3] pio6[4] ] pio6[5] ] pio6[6] pio6[7] pio7[0] pio7[1] pio7[2] gnd vdd pio7[3] pio7[4] pio7[5] pio7[6]/ nbreq pio8[0]/dbgack pio8[1]/dbgrq pio8[2]/dbgen pio8[3]/tck pio8[4]/ tms pio8[5]/ ntrst pio8[6]/tdo pio8[7]/tdi pio7[7]/ nback xd1 xd0 vdd gnd nea nefiq pio0[7]/xa23 pio0[6]/xa22 pio0[5]/xa21 pio0[4]/xa20 pio0[2]/xa18 pio0[3]/xa19 pio0[1]/xa17 pio0[0]/xa16 vdd gnd xa15 xa14 xa13 xa12 xa11 xa10 xa9 xa8 vdd xa7 gnd xa6 gnd xa5 xa4 xa3 xa2 xa0/nlb xa1 vdd xd2 xd3 xd4 xd5 xd6 xd7 gnd vdd pio1[0]/xd8 pio1[1]/xd9 pio1[2]/xd10 pio1[3]/xd11 vdd nrd nwre/ nwrl pio2[0]/ nwl/ nwe pio1[4]/xd12 gnd vdd pio3[0]/ neir[0] pio3[5]/ neir[5] pio3[6]/ neir[6] pio3[7]/ neir[7] gnd pio4[0]/tmin[0]/tmout[0] pio4[1]/tmin[1]/tmout[1] pio4[2]/tmin[2]/tmout[2] pio4[3]/tmin[3]/tmout[3] pio4[4]/tmin[4]/tmout[4] pio4[5]/tmin[5]/tmout[5] pio4[6]/tmclk[0] pio4[7]/tmclk[1] gnd vdd pio5[0]/csi0_sclk osc0 osc1 vdd clkout fsel vcom pllen gnd nrst agnd ai[7] ai[6] ai[5] pio1[5]/xd13 pio1[6]/xd14 pio1[7]/xd15 pio2[1]/ ncas/ ncasl pio2[2]/nras0 pio2[3]/ nwh/ ncash pio2[4]/nras1 pio2[5]/ nhb/ nwrh pio2[6]/ncs1 pio2[7]/ nxwait gnd pio3[1]/ neir[1] pio3[2]/ neir[2] pio3[4]/ neir[4] pio3[3]/ neir[3] pio5[1]/csi0_rxd pio5[2]/csi0_txd pio5[3]/csi1_sclk pio5[4]/csi1_rxd pio5[5]/csi1_txd pio5[6]/asi_rxd pio5[5]/asi_txd gnd ncs0
semiconductor m l670100 / 27 4 pin descriptions type signal name i/o direction description address bus xa23 - xa16 output these are bits 23-16 of the external address bus. they represent secondary functions for i/o port pio0[7:0]. xa15 - xa0 output these are bits 15 - 0 of the external address bus. data bus xd15 - xd8 bidirectional these are bits 15-8 of the external data bus. they represent secondary functions for i/o port pio1[7:0]. xd7- -xd0 bidirectional these are bits 7-0 of the external data bus. bus n cs0 output this output is the chip select signal for bank 0. control signals n cs1 output this output is the chip select signal for bank 1. it represents a secondary function for i/o port pio2[6]. n rd output this output is the read signal for sram banks (0 and 1). n wrl output this output is the write enable low signal for sram banks (0 and 1). n wrh output this output is the write enable high signal for sram banks (0 and 1). it represents a secondary function for i/o port pio2[5]. n wre output this output is the write enable signal for sram banks (0 and 1). n lb output this output is the low byte select signal for sram banks (0 and 1). n hb output this output is the high byte select signal for sram banks (0 and 1). it represents a secondary function for i/o port pio2[5]. n ras0 output this output is the row address strobe signal for bank 2. it represents a secondary function for i/o port pio2[2]. n ras1 output this output is the row address strobe signal for banks 3. it represents a secondary function for i/o port pio2[4]. n casl output this output is the column address strobe low signal for dram banks (2 and 3). it represents a secondary function for i/o port pio2[1]. n cash output this output is the column address strobe high signal for dram banks (2 and 3). it represents a secondary function for i/o port pio2[3]. n we output this output is the write enable signal for dram banks (2 and 3). it represents a secondary function for i/o port pio2[0]. n cas output this output is the column address strobe signal for dram banks (2 and 3). it represents a secondary function for i/o port pio2[1]. n wh output this output is the write enable high signal for dram banks (2 and 3). it represents a secondary function for i/o port pio2[3]. n wl output this output is the write enable low signal for dram banks (2 and 3). it represents a secondary function for i/o port pio2[0]. n xwait input this input pin controls insertion of wait cycles. it represents a secondary function for i/o port pio2[7].
semiconductor m l670100 / 27 5 pin descriptions (cont.) type signal name i/o direction description bus control n breq input this input is a bus request signal from an external device. it represents a secondary function for i/o port pio7[6]. signals n back output this output is an acknowledgment signal to a bus request signal from an external device. it represents a secondary function for i/o port pio7[7]. interru- pts n efiq input this input is an external fast interrupt request (fiq). when accepted, the request is processed as an fiq exception. n eir[7:0] input this inputs are external interrupt requests. they represent secondary functions for i/o port pio3[7:0]. timers tmin[5:0] input these pins function as capture trigger input pins for flexible timer channels 5-0 in capture mode. they represent secondary functions for i/o port pio4[5:0]. tmout[5:0] output these pins function as output pins for flexible timer channels 5-0 in compare output or pwm mode. they represent secondary functions for i/o port pio4[5:0]. tmclk[1:0] input these pins function as flexible timer channels 1 and 0 clock input pins. they represent secondary functions for i/o port pio4[7:6]. serial ports asi_txd output this output is the transmit data for the asynchronous serial interface. it represents a secondary function for i/o port pio5[7]. asi_rxd input this input is the receive data for the asynchronous serial interface. it represents a secondary function for i/o port pio5[6]. csi0_txd output this output is the transmit data for the clock synchronous serial interface 0. it represents a secondary function for i/o port pio5[2]. csi0_rxd input this input is the receive data for the clock synchronous serial interface 0. it represents a secondary function for i/o port pio5[1]. csi0_sclk bidirectional this pin accepts/provides clock signal for the clock synchronous serial interface 0. it represents a secondary function for i/o port pio5[0]. csi1_txd output this output is the transmit data for the clock synchronous serial interface 1. it represents a secondary function for i/o port pio5[5]. csi1_rxd input this input is the receive data for the clock synchronous serial interface 1. it represents a secondary function for i/o port pio5[4]. csi1_sclk bidirectional this pin accepts/provides clock signal for the clock synchronous serial interface 1. it represents a secondary function for i/o port pio5[3].
semiconductor m l670100 / 27 6 pin descriptions (cont.) type signal name i/o direction description analog- to-digital vref input this input is the reference voltage for the analog-to-digital converter channels 7-0. connect it to vdd. converter ai[7:0] input these are analog signal input pins for analog-to-digital converter channels 7-0. debugg- ing tdi input this input is the serial data input for the debugging scan circuit. it represents a secondary function for i/o port pio8[7]. interface tdo output this output is the serial data output for the debugging scan circuit. it represents a secondary function for i/o port pio8[6]. n trst input "l" level input to this pin resets the debugging scan circuit. it represents a secondary function for i/o port pio8[5]. tms input this input selects the mode for the debugging scan circuit. it represents a secondary function for i/o port pio8[4]. tck input this input is the serial clock input for the debugging scan circuit. it represents a secondary function for i/o port pio8[3]. dbgen input "h" level input to this pin enables the cpu's debugging function. it represents a secondary function for i/o port pio8[2]. dbgrq input this input is a debugging request signal from an external device. it represents a secondary function for i/o port pio8[1]. dbgack output this output is an acknowledgment signal to a debugging request signal from an external device. it represents a secondary function for i/o port pio8[0]. i/o ports pio8[7:0] bidirectional these form an 8-bit i/o port. i/o directions are specified at the bit level. pio7[7:0] bidirectional these form an 8-bit i/o port. i/o directions are specified at the bit level. pio6[7:0] bidirectional these form an 8-bit i/o port. i/o directions are specified at the bit level. pio5[7:0] bidirectional these form an 8-bit i/o port. i/o directions are specified at the bit level. pio4[7:0] bidirectional these form an 8-bit i/o port. i/o directions are specified at the bit level. pio3[7:0] bidirectional these form an 8-bit i/o port. i/o directions are specified at the bit level. pio2[7:0] bidirectional these form an 8-bit i/o port. i/o directions are specified at the bit level. pio1[7:0] bidirectional these form an 8-bit i/o port. i/o directions are specified at the bit level. pio0[7:0] bidirectional these form an 8-bit i/o port. i/o directions are specified at the bit level.
semiconductor m l670100 / 27 7 pin descriptions (cont.) type signal name i/o direction description clock control osc0 input this pin is for connecting a crystal oscillator. if an external clock is used, supply it to this pin. osc1 output this pin is for connecting a crystal oscillator. if an external clock is used, leave this pin open. clkout output this output is the internal system clock signal. fsel input connect this pin to vdd or ground to indicate the frequency range for the basic clock. pllen input connect this pin to vdd to enable the built-in phase-looked loop. if the pll is not used because an external clock with a guaranteed duty is available, connect this pin to ground. vcom input this input controls the oscillation frequency of the pll's voltage-controlled oscillator. connect it to ground. system control n rst input "l" level input to this pin produces an external system reset for this lsi. "h" level input then causes execution to resume from address 0x000000. dbsel input during a system reset of this lsi, this input specifies the width of the external data bus for bank 0. connect this pin to vdd for a data bus width of 16bits and to ground for 8bits. n ea input during a system reset of this lsi, this input controls the use of the internal rom. connect this pin to vdd to enable the rom and to ground to disable it. test input during a system reset of this lsi, this input controls the initial pin functions for the i/o port 8 pins(pio8[7:0]). connect this pin to vdd to initialize the port for its secondary function, the debugging interface, and to ground for i/o. power supply vdd input these pins are this lsi's power supply pins. connect them all to vdd. gnd input these pins are this lsi's ground pins. connect them all to ground. avdd input this pin is the analog-to-digital converter's power supply. connect it to vdd. agnd input this pin is the analog-to-digital converter's ground pin. connect it to ground.
semiconductor m l670100 / 27 8 outline of peripheral functions i/o ports the i/o ports consist of nine 8-bit ports: pion(n=0 - 8). i/o directions are specified at the bit level. when configured for input, the pins use high-impedance input. flexible timer the flexible timer consists of six 16-bit timer channels. each channel offers independent choice of four operating modes and of eight count clocks. - timer operating modes - auto-reload timer - compare output - pulse width modulation (pwm) - capture input - timer synchronization - timer channels can be started and stopped in union. - external clocks - timer channels 0 and 1 accept external clock signals. time base generator the time base generator consists of the time base counter, a frequency divider which derives the time base signals for the on-chip peripherals from the system clock signals, and watchdog timer, which counts time base clock cycles and produces a system reset signal when its internal counter overflows. asynchronous serial interface the asynchronous serial interface is a serial port that frames each character of information with start and stop elements. parameters control transfer speed (using a dedicated baud rate generator), character length, number of stop bits and use of parity. - built-in baud rate generator - character length: 7 or 8 bits - stop bits: 1 or 2 - parity: none, odd, or even - error detection for receiving: parity, framing and overrun errors - full duplex operation clock synchronous serial interface the clock synchronous serial interface are two channels of serial ports that transmit 8-bit data synchronized with internal or external clock signals.
semiconductor m l670100 / 27 9 analog-to-digital converter the analog-to-digital converter is an 8-bit successive approximation analog-to-digital converter with eight input channels and four result registers. it offers two operating mode: scan mode, which sequentially converts the inputs from the selected set of four input channels, and select mode, which converts the input from a single input channel. - resolution: 8 bits - eight analog input channels -four result registers for holding conversion results -operating modes - scan modes: sequential conversion of the analo g inputs from the upper or lower set of four input channels - select mode: conversion of the analog inputs from a single input channel interrupt controller the interrupt controller manages interrupt requests from 9 external sources and 19 internal ones and passes them on to the cpu as interrupt request (irq) or fast interrupt request (fiq) exception requests. it supports eight interrupt levels for each source for use in priority control. - the interrupt controller supports 9 external interrupt sources connected to n efiq and n eir[7:0] pins and 19 internal interrupt sources, including the serial ports and the flexible timer channels. - the interrupt controller simplifies interrupt priority control with a choice of eight interrupt levels for each source. - the interrupt controller assigns a unique interrupt number to each source to permit rapid branching to the appropriate routine. external memory controller the external memory controller generates control signals for accessing external memory (rom, sram, dram, etc.), and other devices with address in the external memory space. - support for direct connection of rom, sram and i/o devices - strobe signal outputs for a variety of memory and i/o devices - support for direct connection of dram - multiplexed row and column addresses - random access and high-speed paged modes - programmable wait cycle insertion - memory space divided into four banks - two banks for rom, sram and i/o devices - two banks for dram - address space of 16 megabytes for each bank - separate data bus width (8 or 16 bits), wait cycle, and off time setting for each bank - single-stage store buffer permitting internal access during a wait cycle to external memory or device - arbitration of external bus requests from external devices
semiconductor m l670100 / 27 10 c lock controller the clock controller controls the oscillator circuit based on a crystal oscillator and a built-in phase-locked loop which together generate and control the system clock signal. it offers a choice of divider ratio (1/1, 1/2 and 1/4) for adjusting operating clock frequency to ma tch the load of processing. it also controls the transitions to and from a stand-by mode, halt mode .
semiconductor m l670100 / 27 11 configurations of pins and i/o ports input pins ( n rst, n ea, dbsel, test, n efiq, fsel, pllen, vcom) output pin (clkout) tri-state output pins (xa23 - xa1, n lb/xa0, n cs0, n rd, n wre/ n wrl) bidirectional pins (xd7 - xd0) vdd gnd input pins (high impedance) bidirectional pins (cmos output when enabled) output enable signal read signal vdd gnd output pin (cmos out p ut) output pins (cmos output when enabled) output enable signal
semiconductor m l670100 / 27 12 i/o port a (i/o ports without second functions) pio6[7:0], pio7[5:0] i/o port b (i/o ports with second functions of input) pio2[7], pio3[7:0] , pio4[7:6] , pio5[6] , pio5[4], pio5[1] , pio7[6] , pio8[7] , pio8[5:1] pmm [n] pom [n] piom [n] peripheral bus read pim [n] pmm [n] pom [n] piom [n] peripheral bus read pim [n] pfsm [n] secondary function input signal
semiconductor m l670100 / 27 13 i/o port c (i/o ports with second functions of output) pio5[7], pio5[5], pio5[2], pio7[7], pio8[6], pio8[0] pmm [n] pom [n] piom [n] peripheral bus read pim [n] pfsm [n] secondary function output signal
semiconductor m l670100 / 27 14 i/o port d (i/o ports with second functions of tri-state output) pio0[7:0], pio2[6:0] pmm [n] pom [n] piom [n] peripheral bus read pim [n] pfsm [n] secondary function output signal secondary function output enable signal
semiconductor m l670100 / 27 15 i/o port e (i/o ports with second functions of input and output) pio1[7:0], pio4[5:0], pio5[3], pio5[0] pmm [n] pom [n] piom [n] peripheral bus read pim [n] pfsm [n] secondary function output signal secondary function output enable signal secondary function input signal
semiconductor m l670100 / 27 16 electrical characteristics absolute maximum ratings item symbol condition rated value unit power supply v dd - 0.3 to 4.6 v input voltage v in v dd =av dd =v ref - 0.3 to v dd + 0.3 analog input voltage v ai gnd=agnd=0v - 0.3 to av dd + 0.3 v output current i o 12 ma power dissipation p d ta=25v 850 mw storage temperature t stg - - 55 to + 150 c recommended operating conditions (condition: gnd=agnd=0v ) item symbol condition min. typ. max. unit power supply v dd - 2.7 3.3 3.6 analog power supply av d d v dd =av dd 2.7 3.3 3.6 v analog reference voltage v ref - av dd -0.3 - av dd analog input voltage v ai - agnd - v ref operating frequency 1 f c1 v dd =3.0 to 3.6 v , 1 4 - 25 operating frequency 2 f c2 v dd =2.7 to 3.6 v , 2 4 - 20 mhz ambient temperature t a - - 40 25 + 85 c 1 basic clock frequency from the oscillator circuit or an external clock signal pllen input fsel input operating frequency 1 f c1 4 - 6.25mhz ? h ? level ? h ? level (connect to v dd ) 4 - 25mhz 8 - 12.5mhz (connect to v dd ) ? l ? level (connect to gnd ) 4 - 25mhz 4 - 25mhz (external clock only) ? l ? level (connect to gnd ) ? h ? level (connect to v dd ) or ? l ? level (connect to gnd ) 4 - 25mhz 2 basic clock frequency from the oscillator circuit or an external clock signal pllen input fsel input operating frequency 2 f c2 4 - 5mhz ? h ? level ? h ? level (connect to v dd ) 4 - 20mhz 8 - 10mhz (connect to v dd ) ? l ? level (connect to gnd ) 4 - 20mhz 4 - 20mhz (external clock only) ? l ? level (connect to gnd ) ? h ? level (connect to v dd ) or ? l ? level (connect to gnd ) 4 - 20mhz
semiconductor m l670100 / 27 17 dc characteristics (condition: v dd = av dd = v ref = 2.7v to 3.6v , gnd = agnd=0v, ta =- 40 to + 85 c) item symbo l condition min. typ. max. unit high level input voltage 1 v ih1 1 0.65x v dd - v dd +0.3 high level input voltage 2 v ih2 2 2 - v dd +0.3 low level input voltage 1 v il1 1 -0.3 - 0.3x v dd low level input voltage 2 v il2 2 -0.3 - 0.8 high level output voltage v oh i oh =-4m a i oh =-100 ua 2. 2( * 2) v dd -0.2 - - - - low level output voltage v ol i ol = 4ma - - 0.4 v input leak current 1 |i li | v i =0/v dd ,3 - - 2.0( * 3) input leak current 2 |i l 2 | v i =0/v dd ,4 - - 10.0( * 3) output leak current |i lo | v o =0/v dd - - 2.0( * 3) m a input capacity c i - - 6 - output capacity c o - - 9 - input/output capacity c io - - 10 - m f power consumption (in halt mode) i ddh - 30 50 power consumption i dd f c = 25 m hz no load - 60 100 ma 1 applied to pio8 - pio0, xd7 - xd0, nefiq 2 applied to nrst, nea, dbsel, test, fsel, pllen, vcom 3 applied to input pins other than osc0 4 applied to osc0 ( * 1): typ. means that v dd =3.3v, ta=25 c ( * 2): 2.4v in case of that v dd = av dd = v ref = 3.0 to 3.6v ( * 3): 2 0 m a in case of that t a is equal or greater than 50 c
semiconductor m l670100 / 27 18 ac characteristics (condition: v dd = av dd = v ref = 2.7v to 3.6v , gnd=agnd=0v,ta =-40 to + 85 c) clock timing item symbol condition min. typ. max. unit clock frequency f c 4 - 25 mhz clock cycle time t c 40 - 250 clock high level pulse width t ch 16 - - clock low level pulse width t cl 16 - - ns external clock frequency f exc 4 - 25 mhz external clock cycle time t exc 40 - 250 external clock high level pulse width t exch 16 - - external clock low level pulse width t excl v dd =3.0 to 3.6 v 16 - - ns clock frequency f c 4 - 20 mhz clock cycle time t c 50 - 250 clock high level pulse width t ch 20 - - clock low level pulse width t cl 20 - - ns external clock frequency f exc 4 - 20 mhz external clock cycle time t exc 50 - 250 external clock high level pulse width t exch 20 - - external clock low level pulse width t excl v dd =2.7 to 3.6 v 20 - - clock rise time t r - - - 5 clock fall time t f - - - 5 external clock rise time t exr - - - 5 external clock fall time t exf - - - 5 ns
semiconductor m l670100 / 27 19 control signals timing item symbol condition min. typ. max. unit nrst pulse width ( * 1) t rstw1 - 2t c - - ns nrst pulse width ( * 2) t rstw2 oscillation stable time - - - nefiq pulse width t efiqw - 2t c - - neir pulse width t eirw - 2t c - - tmin pulse width t tminw - 2t c - - tmclk pulse width t tmclkw - 2t c - - ns sclk frequency f sc - - - 1/8f c mhz sclk high level pulse width t sclkh - 4t c - - sclk low level pulse width t sclkl - 4t c - - txd delay time t txd c l =50pf - - 1t c +22 rxd set-up time t rxs - 0.5t c - - rxd hold time t rxh - 1.5t c - - dbgrq set-up time t rqs - 1.0 - - dbgrq hold time t rqh - 2.6 - - dbgack delay time t dbgd c l =50pf 2.4 - 15.2 ns ( * 1): not applied to power-on. ( * 2): applied to power-on.
semiconductor m l670100 / 27 20 external bus timing item symbol condition min. typ. max. unit xa[23:1],nlb/xa0 delay time t xad 3 - 14 xd[15:0] output delay time t xdod 5 - 20 xd[15:0] input set-up time t xdis 11 - - xd[15:0] input hold time t xdih 0 - - nxwait set-up time t xwaits 3 - - nxwait hold time t xwaith 0 - - nhb delay time t hbd 2 - 12 ncs[1:0] delay time t csd 2 - 11 nwre,nwrh,nwrl delay time t wrd 3 - 12 nrd delay time t rdd 4 - 11 nras[1:0] delay time t rasd 3 - 12 ncas delay time t casd 3 - 13 nwe,nwh,nwl delay time t wed 2 - 12 nbreq set-up time t breqs 5 - - nbreq hold time t breqh 3 - - nback delay time t backd 4 - 13 high-impedance delay time t xhd c l =50pf 4 - 13 ns
semiconductor m l670100 / 27 21 clock timing control signals timing t sclkl t sclkh t txd t rxs t rxh sclk txd rxd t c t ch t cl t r t f t exc t exch t excl t exr t exf clkout external clock n efiq n eir n rst t rstw1, t rstw2 t efiqw , t eirw t tminw , t tmclkw tmin tmck
semiconductor m l670100 / 27 22 control signals timing (cont.) t dbgd t rqs t rqh clkout dbgack dbgrq
semiconductor m l670100 / 27 23 external bus timing bank 0 and bank 1 write cycle timing t hbd t xad t xad t hbd t csd t csd t wrd t wrd t xdod t xdod write data clkout xa23-1 n lb/xa n hb n cs0 n cs1 n wre n wrl n wrh xd15-0
semiconductor m l670100 / 27 24 bank 0 and bank 1 read cycle timing t hbd t xad t xad t hbd xd15-0 t csd t csd t rdd t rdd t xdis t xdih read data clkout xa23-1 n lb/xa n hb n cs0 n cs1 n rd
semiconductor m l670100 / 27 25 bank 2 and bank 3 read/write cycle timing cas before ras (cbr) refresh t xad t rasd t rasd t casd t casd t xdis t xdih t xad t xdod t xdod t wed t wed clkout xa23-1 n lb/xa n ras0 n ras1 n cas n casl n cash xd15-0 (read cycle) xd15-0 (write cycle) n we, n wl n wh (write cycle) t rasd t rasd t casd t casd clkout n ras n cas
semiconductor m l670100 / 27 26 self refresh n xwait input timing external bus release timing t xwaits t xwaith clkout n xwait clkout n ras n cas t rasd t rasd t casd t casd t breqs t breqh clkout n breq clkout n back t backd t backd t xhd t x hd xa xd control signals
semiconductor m l670100 / 27 27 a-to-d converter characteristics (condition: v dd = av dd = v ref = 2.7v to 3.6v , gnd=agnd=0v,ta=-40 to +85 c ) item symbol condition min. typ. max. unit resolution n - - 8 bit linearity error e l refer to the following -3.0 - +3 .0 lsb differential linearity error e d recommended circuit. analog input source impedance - 1.0 - + 1.0 lsb zero scale error e zs r i is equal or less than 5k w - - +2.0 lsb full scale error e fs - - -2.0 lsb conversion time t conv f c =25mhz - 10.68 - m s/ch definitions of terms resolution the minimum distinguishable analog value. for 8 bits, 2 8 =256, i.e.(vref-agnd)/256. linearity error variance between the ideal conversion characteristics as an 8-bit a-to-d converter and actual conversion characteristics (does not include quantatized error). differential linearity error indicates the smoothness of the conversion. the width of analog input voltage corresponding to the change by one bit of digital output is 1lsb=(vref-agnd)/256 ideally. the variance between this ideal bit size and bit size at arbitrary point in the conversion range. zero scale error variance between the ideal conversion characteristics at the switching point of digital output ? 0x00 ? - ? 0x01 ? and actual conversion characteristics. full scale error variance between the ideal conversion characteristics at the switching point of digital output ? 0xfe ? - ? 0xff ? and actual conversion characteristics. r i (analog input source impedance) is equal or less than 5k w 0.1 m f 0.1 m f 3.3v analog input 0.1 m f 0.1 m f 47 m f + r i + - ML670100 v re f v dd ai[7:0] gnd agnd av dd 47 m f + 3.3v 0v

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